The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device having a redundant configuration.
In order to increase an integration degree of a semiconductor memory device, it is possible to employ a redundant configuration which improves the yield rate markedly. Especially, as for a MOS memory device having a high integration degree, the redundant configuration has been adopted since the time of 64K SRAM. The integration degree in an ECL RAM has also been increased year by year and, especially in recent years, due to the advancement of Bi-CMOS technique. The adoption of a redundant configuration makes it possible to replace a row or column having a fault bit by a spare row or column, whereby a chip having a small number of fault bits can be made substantially faultless. The essentials for a redundant configuration include the above-mentioned spare row or column, an address comparator which compares the address of a fault bit with a selected address and generates a signal by which the row or column having the fault bit, if any, is left out of selection and the spare row or column is brought into a selected state, and a roll call circuit which detects the address of any fault bit.
A power supply current is small in the roll call circuit of a MOS memory device and, due to this characteristic, a small increase in the current can detect the address of a fault bit. The power supply current is increased one by one from "0" address to the final address and is measured in each address. When the address of a fault bit is detected, the address comparator operates and generates the signal, which results in an increase in the power supply current of about 1 mA. In the case of an ECL RAM, the power supply current is about 100 mA so that it is impossible to use the roll call circuit of this type which detects an address of a fault bit by detecting the increase of a power supply current. A conventional method of detecting an address of a fault bit is that of detecting the current of an input terminal. This conventional method, however, has a disadvantage in that, when a spare memory is accessed, the amount of the power supply current increase is so small that the measurement of the current is affected by the contact resistance between the input terminal and the measuring device which measures the current of the terminal resulting in measurement errors, and also in that, in the case of a memory device having a plurality of outputs, the address of a fault bit cannot be detected in every output thereof.